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Level 3 cache not detected
Posted: Sat Jul 02, 2022 4:42 pm
by Corporal Up The Nuts
My G4 cpu module has the two CY7C1354BV25-166AXC SRAM chips installed, but neither Ranger and Sysmon is able to detect it.
I've heard that early in the production of the A1XE that they removed the cache to save costs, but does AmigaOS also disable it since then?
Any way to re-enable it?
Re: Level 3 cache not detected
Posted: Sun Jul 10, 2022 11:19 am
by sailorMH
I am not sure, but it can be caused by this:
AmigaOne XE and Micro A1-C had Southbridge Articia-S with cache coherency bug. There is software workaround in OS. It is possible, that it also turns off L3. Try to search for Articia S cache coherency or ask directly developers.
Re: Level 3 cache not detected
Posted: Fri Aug 05, 2022 2:48 pm
by tonyw
Long time ago now, but back in 2004 I do remember the kernel developers saying that the Level 3 cache had little or no effect, and was disabled because of that.
Re: Level 3 cache not detected
Posted: Fri Jun 23, 2023 8:57 pm
by sailorMH
I know, I am replying to older topics.
But if L3 cache on our G4 modules are disabled by developers decision that L3 has no effect, it is not exact.
L3 has in real world great effect for certain tasks: There
https://www.amigaportal.cz/node/162841 is mine + ervus@macrumors article about L1-L3 caches in powerpc G3-G5 CPUs, with measuring of G4 L3 cache size influence from ervus and G3 L2 cache size influence from me. Results are very impressive.
Article is in Czech language, so please use google translate.
So, if L3 cache on our modules is only switched-off, I plead for enabling of L3, it is great.
But if it caused by ArticiaS cache coherency problem, it is a pitty, we cannot do nothing.
Re: Level 3 cache not detected
Posted: Sun Jul 02, 2023 2:04 pm
by Hypex
I wonder then if it's still enabled in Linux?
Re: Level 3 cache not detected
Posted: Sun Aug 27, 2023 7:26 pm
by sailorMH
Hypex wrote: Sun Jul 02, 2023 2:04 pm
I wonder then if it's still enabled in Linux?
Unfortunatelly, even L2 is disabled - probably it "solves" cache coherency problem:
Code: Select all
root@xe:/home/martina# lshw
xe
description: Computer
product: AmigaOne
width: 32 bits
*-core
description: Motherboard
physical id: 0
capabilities: eyetech_amigaone
*-cpu
description: CPU
product: 7455, altivec supported
physical id: 0
bus info: cpu@0
version: 3.3 (pvr 8001 0303)
size: 400MHz
clock: 133MHz
*-cache
description: L1 Cache
physical id: 0
size: 32KiB
root@xe:/home/martina# lscpu
Architecture: ppc
CPU op-mode(s): 32-bit
Byte Order: Big Endian
CPU(s): 1
On-line CPU(s) list: 0
Thread(s) per core: 1
Core(s) per socket: 1
Socket(s): 1
Vendor ID: Eyetech Ltd.
Model: AmigaOne
BogoMIPS: 66.66
L1d cache: 32K
L1i cache: 32K
P.S.: 400MHz is a (probably firmware) bug - it shows 400, but in real it is 1400 MHz.
Re: Level 3 cache not detected
Posted: Mon Aug 28, 2023 4:13 pm
by Hypex
sailorMH wrote: Sun Aug 27, 2023 7:26 pm
Unfortunatelly, even L2 is disabled - probably it "solves" cache coherency problem:
Well that would. But it tends to be on for an XE. For example, if radeon module uses acceleration, it will freeze up as cache is activated normally.
It is strange getting the CPU clock wrong. Though checking out lshw I've seen "size" for base speed and 'capacity" for max speed. So I wonder perhaps if it estimated a base and not a nominal speed.
Re: Level 3 cache not detected
Posted: Mon Aug 28, 2023 9:11 pm
by sailorMH
Hypex wrote: Mon Aug 28, 2023 4:13 pm
But it tends to be on for an XE. For example, if radeon module uses acceleration, it will freeze up as cache is activated normally.
And is possible to enable L2 with some kernel parameter? Like l2cr or cachesize= ? Or is it done by parameters during kernel compilation?
Hypex wrote:
It is strange getting the CPU clock wrong. Though checking out lshw I've seen "size" for base speed and 'capacity" for max speed. So I wonder perhaps if it estimated a base and not a nominal speed.
Yes, it is strange. I have no simple answer, but higher frequencies ( with PLL_CFG_4 = 1 ) shows false CPU frequency. U-Boot, AmigaOS and linux also.
1400 MHz shows like 400 MHz
1533 MHz shows like 66 MHz, i.e. like value with PLL_CFG_4 = 0
But CPU speed is high for sure.
I tried other UBoot versions, but every shows false speed. Maybe is it caused by my 7455 CPU? Evillords's 7457 shows 1533 normally.
Here
https://www.amigaportal.cz/node/161812 ( Czech language ) is my experiences with AmigaOne XE CPU exchange and overclock.
Generally, it is not big problem, XE is fast now.
I am suspicious about UBoot. MacMini has the same problem with heavy overclocking, some OF variables must be modified to show correct frequency.
Re: Level 3 cache not detected
Posted: Mon Aug 28, 2023 9:34 pm
by sailorMH
I checked commandline kernel parameters, and there are l2cr=0x80000000
My 7455 has 256 kB L2, i.e. 0x40000 and 0x80000000 is 2 GB...
Unfortunatelly, I am not find what does this mean. I can try l2cr=0x40000....
P.S. if l2cr kernel parameter set the L2CR CPU register ( L2 control register ), setting of this is too complex for me.. Chapter 2.2.5.5 of MPC7450 RISC Microprocessor Family Reference Manual
https://www.nxp.com/docs/en/reference-m ... 7450UM.pdf 
Re: Level 3 cache not detected
Posted: Tue Aug 29, 2023 8:24 am
by sailorMH
After quick look on manual, the most simple setting of l2cr should be:
l2cr=3 .. i.e. 11B
it means L2 cache is enabled + L2 parity checking enabled
But, kernel parameter meaning should differ from CPU l2cr register and maybe other L2 parameters should be set. But this I don't understand.
I will try l2cr=3 on weekend and we will see.