Kernel 5.13

AmigaOne X5000 platform specific issues related to Linux only.
User avatar
xeno74
Posts: 7022
Joined: Fri Mar 23, 2012 7:58 am

Re: Kernel 5.13

Post by xeno74 »

Today, I will try it again with skipping the steps with the boot issue.
  1. Code: Select all

    git bisect start -- arch/powerpc
  2. Code: Select all

    git bisect good 887f3ceb51cd3~
  3. Code: Select all

    git bisect bad c70a4be130de333ea079c59da41cc959712bb01c
  4. git bisect bad
  5. git bisect skip It stopped after loading the dtb and uImage. Maybe a third bug.
  6. git bisect skip It stopped after loading the dtb and uImage.
  7. git bisect skip It stopped after loading the dtb and uImage.
  8. git bisect skip It stopped after loading the dtb and uImage.
  9. git bisect skip It stopped after loading the dtb and uImage. ([472724111f0f72042deb6a9dcee9578e5398a1a1] powerpc/iommu: Enable remaining IOMMU Pagesizes present in LoPAR)
  10. git bisect skip It stopped after loading the dtb and uImage. ([ceff77efa4f8d9f02d8442171b325d3b7068fe5e] powerpc/64e/interrupt: Use new interrupt context tracking scheme)
  11. git bisect skip It stopped after loading the dtb and uImage. ([7dcc37b3eff97379b194adb17eb9a8270512dd1d] powerpc/xive: Map one IPI interrupt per node)
  12. git bisect skip It stopped after loading the dtb and uImage. ([097157e16cf8bf91b9cf6fbda05d234d3599c01f] powerpc/64e/interrupt: reconcile irq soft-mask state in C)
  13. git bisect skip It didn't compile.
    Error messages:

    Code: Select all

    arch/powerpc/kernel/interrupt.o: In function `.syscall_exit_prepare':
    interrupt.c:(.text+0x278): undefined reference to `.schedule_user'
    arch/powerpc/kernel/interrupt.o: In function `.interrupt_exit_user_prepare':
    interrupt.c:(.text+0x340): undefined reference to `.schedule_user'
    Makefile:1199: recipe for target 'vmlinux' failed
    make: *** [vmlinux] Error 1
    
    ([fd6db2892ebaa1383a93b4a609c65b96e615510a] powerpc/xive: Modernize XIVE-IPI domain with an 'alloc' handler)
  14. git bisect skip It stopped after loading the dtb and uImage. ([0c2472de23aea5ce9139a3e887191925759d1259] powerpc/64e/interrupt: use new interrupt return)
  15. git bisect skip It stopped after loading the dtb and uImage. ([097157e16cf8bf91b9cf6fbda05d234d3599c01f] powerpc/64e/interrupt: reconcile irq soft-mask state in C)
  16. git bisect skip It didn't compile.
    Error messages:

    Code: Select all

    arch/powerpc/kernel/interrupt.o: In function `.syscall_exit_prepare':
    interrupt.c:(.text+0x278): undefined reference to `.schedule_user'
    arch/powerpc/kernel/interrupt.o: In function `.interrupt_exit_user_prepare':
    interrupt.c:(.text+0x340): undefined reference to `.schedule_user'
    Makefile:1199: recipe for target 'vmlinux' failed
    make: *** [vmlinux] Error 1
    
    ([14b3c9d24a7a5c274a9df27d245516f466d3bc5f] powerpc/syscalls: switch to generic syscalltbl.sh)
  17. git bisect skip It stopped after loading the dtb and uImage. ([08a022ad3dfafc7e33d4529015e14bb75179cacc] powerpc/powernv/memtrace: Allow mmaping trace buffers)
  18. git bisect skip It stopped after loading the dtb and uImage. ([e5d56763525e65417dad0d46572b234fa0008e40] powerpc/rtas: rename RTAS_RMOBUF_MAX to RTAS_USER_REGION_SIZE)
  19. git bisect skip It stopped after loading the dtb and uImage. ([98db179a78dd8379e9d2cbfc3f00224168a9344c] powerpc/64s: power4 nap fixup in C)
  20. git bisect skip It stopped after loading the dtb and uImage. ([c13ff6f3251318f5e1ff5b1a6d05f76996db672a] powerpc/rtas: improve ppc_rtas_rmo_buf_show documentation)
  21. git bisect skip It stopped after loading the dtb and uImage. ([2e2a441d2c0bb639b6fdbb64b15ee0a43599bcec] powerpc/perf: Infrastructure to support checking of attr.config*)
  22. git bisect skip It stopped after loading the dtb and uImage. ([0649cdc8237943c15fc977e96033dc8ae28cc2bd] powerpc/rtas: move syscall filter setup into separate function)


Cheers,
Christian
http://www.amigalinux.org
http://www.supertuxkart-amiga.de

Running Linux on AmigaONEs can require some tinkering.
User avatar
xeno74
Posts: 7022
Joined: Fri Mar 23, 2012 7:58 am

Re: Kernel 5.13

Post by xeno74 »

Hi All,

I downloaded and compiled the latest git kernel for the X5000 today. If I don't use the radeon_nislands_smc patch then it doesn't boot. If I use it then it boots but Xorg restarts again and again (see [FSL P50x0] Xorg always restarts again and again after the the PowerPC updates 5.13-1).

Cheers,
Christian
http://www.amigalinux.org
http://www.supertuxkart-amiga.de

Running Linux on AmigaONEs can require some tinkering.
User avatar
xeno74
Posts: 7022
Joined: Fri Mar 23, 2012 7:58 am

Re: Kernel 5.13

Post by xeno74 »

Christophe wrote: - Can you check that 887f3ceb51cd with cherry-picked 525642624783 has Xorg working ?
Thanks
Christophe
  • git checkout 887f3ceb51cd
  • git cherry-pick 525642624783
Result: Xorg works.
Christophe wrote: - Can you bisect between 887f3ceb51cd[good] and 56bec2f9d4d0[bad] to identify first bad commit that stops after loading the dtb and uImage ?
- Once that first bad commit is identified, can you check whether the preceeding commit with cherry-picked 525642624783 has Xorg working or not ?

Thanks
Christophe
  1. Code: Select all

    git bisect start
  2. Code: Select all

    git bisect good 887f3ceb51cd
  3. Code: Select all

    git bisect bad 56bec2f9d4d0
  4. git bisect good Xorg restarts again and again but we are looking for the first bad commit that stops the boot after loading the dtb and uImage.
  5. git bisect good Xorg restarts again and again.
  6. git bisect good Xorg restarts again and again.
  7. git bisect good Xorg restarts again and again.
Result:

Code: Select all

56bec2f9d4d05675cada96772a8a93010f4d82bf is the first bad commit
commit 56bec2f9d4d05675cada96772a8a93010f4d82bf
Author: Michael Ellerman <mpe@ellerman.id.au>
Date:   Wed Mar 31 11:38:40 2021 +1100

    powerpc/mm/64s: Add _PAGE_KERNEL_ROX
    
    In the past we had a fallback definition for _PAGE_KERNEL_ROX, but we
    removed that in commit d82fd29c5a8c ("powerpc/mm: Distribute platform
    specific PAGE and PMD flags and definitions") and added definitions
    for each MMU family.
    
    However we missed adding a definition for 64s, which was not really a
    bug because it's currently not used.
    
    But we'd like to use PAGE_KERNEL_ROX in a future patch so add a
    definition now.
    
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/20210331003845.216246-1-mpe@ellerman.id.au

:040000 040000 ff8171830c08e4f99852947a5c3b62e784220a26 85aff144e5219bce4eb6adb2ac32c6459cac22d0 M	arch
git cherry-pick 525642624783

Code: Select all

powerpc/signal32: Fix erroneous SIGSEGV on RT signal return
 Author: Christophe Leroy <christophe.leroy@csgroup.eu>
 Date: Fri Apr 23 13:52:10 2021 +0000
 1 file changed, 2 insertions(+), 2 deletions(-)
Xorg works after compiling with the cherry-pick of 525642624783.
Last edited by xeno74 on Sat May 08, 2021 5:29 pm, edited 1 time in total.
http://www.amigalinux.org
http://www.supertuxkart-amiga.de

Running Linux on AmigaONEs can require some tinkering.
User avatar
xeno74
Posts: 7022
Joined: Fri Mar 23, 2012 7:58 am

Re: Kernel 5.13

Post by xeno74 »

xeno74 wrote: Fri Apr 30, 2021 12:22 pm Hi All,

I compiled the latest Git kernel today. Unfortunately this kernel doesn't boot on the X5000 and X1000 anymore. It boots in a virtual e5500 QEMU machine.

Result of bisect: 434fb1e7444a2efc3a4ebd950c7f771ebfcffa31 is the first bad commit.

Code: Select all

Author: Gustavo A. R. Silva <gustavoars@kernel.org>
Date:   Wed Feb 10 17:49:27 2021 -0600

    drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE
    
    There is a regular need in the kernel to provide a way to declare having
    a dynamically sized set of trailing elements in a structure. Kernel code
    should always use “flexible array members”[1] for these cases. The older
    style of one-element or zero-length arrays should no longer be used[2].
    
    Use flexible-array member in struct NISLANDS_SMC_SWSTATE, instead of
    one-element array.
    
    Also, this helps with the ongoing efforts to enable -Warray-bounds by
    fixing the following warnings:
    
    drivers/gpu/drm/radeon/ni_dpm.c: In function ‘ni_convert_power_state_to_smc’:
    drivers/gpu/drm/radeon/ni_dpm.c:2521:20: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2521 |   smc_state->levels[i].dpm2.MaxPS =
          |   ~~~~~~~~~~~~~~~~~^~~
    drivers/gpu/drm/radeon/ni_dpm.c:2523:20: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2523 |   smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
          |   ~~~~~~~~~~~~~~~~~^~~
    drivers/gpu/drm/radeon/ni_dpm.c:2524:20: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2524 |   smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
          |   ~~~~~~~~~~~~~~~~~^~~
    drivers/gpu/drm/radeon/ni_dpm.c:2525:20: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2525 |   smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
          |   ~~~~~~~~~~~~~~~~~^~~
    drivers/gpu/drm/radeon/ni_dpm.c:2526:35: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2526 |   smc_state->levels[i].stateFlags |=
          |                                   ^~
    drivers/gpu/drm/radeon/ni_dpm.c:2526:35: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2526 |   smc_state->levels[i].stateFlags |=
          |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
     2527 |    ((i != (state->performance_level_count - 1)) && power_boost_limit) ?
          |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     2528 |    PPSMC_STATEFLAG_POWERBOOST : 0;
          |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/radeon/ni_dpm.c:2442:20: warning: array subscript 1 is above array bounds of ‘NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
     2442 |   smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
    
    [1] https://en.wikipedia.org/wiki/Flexible_array_member
    [2] https://www.kernel.org/doc/html/v5.9/process/deprecated.html#zero-length-and-one-element-arrays
    
    Link: https://github.com/KSPP/linux/issues/79
    Link: https://github.com/KSPP/linux/issues/109
    Build-tested-by: kernel test robot <lkp@intel.com>
    Link: https://lore.kernel.org/lkml/6023ed54.BfIY+9Uz81I6nq19%25lkp@intel.com/
    Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

:040000 040000 825941c1622038715917db88900263261697ff43 44e16f7b0c4f28a6ca1fb7cc71a6d6a7a9db668f M	drivers
I was able to revert the first bad commit.

Code: Select all

git revert 434fb1e7444a2efc3a4ebd950c7f771ebfcffa31
Output:

Code: Select all

[master 437344379819] Revert "drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE"
 1 file changed, 5 insertions(+), 5 deletions(-)
After a new compiling, the kernel boots without any problems.

I created a patch for reverting the bad commit:

Code: Select all

diff -rupN a/drivers/gpu/drm/radeon/nislands_smc.h b/drivers/gpu/drm/radeon/nislands_smc.h
--- a/drivers/gpu/drm/radeon/nislands_smc.h     2021-04-30 12:53:11.426435827 +0200
+++ b/drivers/gpu/drm/radeon/nislands_smc.h     2021-04-30 12:52:35.298525162 +0200
@@ -134,11 +134,11 @@ typedef struct NISLANDS_SMC_HW_PERFORMAN

 struct NISLANDS_SMC_SWSTATE
 {
-       uint8_t                             flags;
-       uint8_t                             levelCount;
-       uint8_t                             padding2;
-       uint8_t                             padding3;
-       NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
+    uint8_t                             flags;
+    uint8_t                             levelCount;
+    uint8_t                             padding2;
+    uint8_t                             padding3;
+    NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
 };

 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
The kernel compiles and boots with this patch on my X1000 and X5000.

Cheers,
Christian
Gustavo released a patch today.

Code: Select all


From 4c16031cebe9b4d319974bf86af4f9823f911955 Mon Sep 17 00:00:00 2001
From: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Date: Thu, 6 May 2021 18:28:39 -0500
Subject: drm/radeon/ni_dpm: Fix booting bug

Create new structure NISLANDS_SMC_SWSTATE_SINGLE, as initialState.levels
and ACPIState.levels are never actually used as flexible arrays. Those
arrays can be used as simple objects of type
NISLANDS_SMC_HW_PERFORMANCE_LEVEL, instead.

Currently, the code fails because flexible array _levels_ in
struct NISLANDS_SMC_SWSTATE doesn't allow for code that accesses
the first element of initialState.levels and ACPIState.levels
arrays:

drivers/gpu/drm/radeon/ni_dpm.c:
1690         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1691                 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
...
1903:   table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1904:   table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);

because such element cannot be accessed without previously allocating
enough dynamic memory for it to exist (which never actually happens).

That's why struct NISLANDS_SMC_SWSTATE should only be used as type
for object driverState and new struct NISLANDS_SMC_SWSTATE_SINGLE is
created as type for objects initialState, ACPIState and ULVState.

Also, with the change from one-element array to flexible-array member
in commit 434fb1e7444a ("drm/radeon/nislands_smc.h: Replace one-element
array with flexible-array member in struct NISLANDS_SMC_SWSTATE"), the
size of dpmLevels in struct NISLANDS_SMC_STATETABLE should be fixed to
be NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE instead of
NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1.

Bug: https://lore.kernel.org/dri-devel/3eedbe78-1fbd-4763-a7f3-ac5665e76a4a@xenosoft.de/
Fixes: 434fb1e7444a ("drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE")
Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
---
 drivers/gpu/drm/radeon/ni_dpm.c       | 144 +++++++++++++++++-----------------
 drivers/gpu/drm/radeon/nislands_smc.h |  34 +++++---
 2 files changed, 94 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index dd5ef64937230..769f666335ac4 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -1687,102 +1687,102 @@ static int ni_populate_smc_initial_state(struct radeon_device *rdev,
 	u32 reg;
 	int ret;
 
-	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
+	table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
 		cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
-	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
+	table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL_2 =
 		cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
-	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
+	table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
 		cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
-	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
+	table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 =
 		cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
-	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
+	table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
 		cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
-	table->initialState.levels[0].mclk.vDLL_CNTL =
+	table->initialState.level.mclk.vDLL_CNTL =
 		cpu_to_be32(ni_pi->clock_registers.dll_cntl);
-	table->initialState.levels[0].mclk.vMPLL_SS =
+	table->initialState.level.mclk.vMPLL_SS =
 		cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
-	table->initialState.levels[0].mclk.vMPLL_SS2 =
+	table->initialState.level.mclk.vMPLL_SS2 =
 		cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
-	table->initialState.levels[0].mclk.mclk_value =
+	table->initialState.level.mclk.mclk_value =
 		cpu_to_be32(initial_state->performance_levels[0].mclk);
 
-	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
+	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
-	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
+	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
-	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
+	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
-	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
+	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
-	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
+	table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
-	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
+	table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
 		cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
-	table->initialState.levels[0].sclk.sclk_value =
+	table->initialState.level.sclk.sclk_value =
 		cpu_to_be32(initial_state->performance_levels[0].sclk);
-	table->initialState.levels[0].arbRefreshState =
+	table->initialState.level.arbRefreshState =
 		NISLANDS_INITIAL_STATE_ARB_INDEX;
 
-	table->initialState.levels[0].ACIndex = 0;
+	table->initialState.level.ACIndex = 0;
 
 	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
 					initial_state->performance_levels[0].vddc,
-					&table->initialState.levels[0].vddc);
+					&table->initialState.level.vddc);
 	if (!ret) {
 		u16 std_vddc;
 
 		ret = ni_get_std_voltage_value(rdev,
-					       &table->initialState.levels[0].vddc,
+					       &table->initialState.level.vddc,
 					       &std_vddc);
 		if (!ret)
 			ni_populate_std_voltage_value(rdev, std_vddc,
-						      table->initialState.levels[0].vddc.index,
-						      &table->initialState.levels[0].std_vddc);
+						      table->initialState.level.vddc.index,
+						      &table->initialState.level.std_vddc);
 	}
 
 	if (eg_pi->vddci_control)
 		ni_populate_voltage_value(rdev,
 					  &eg_pi->vddci_voltage_table,
 					  initial_state->performance_levels[0].vddci,
-					  &table->initialState.levels[0].vddci);
+					  &table->initialState.level.vddci);
 
-	ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
+	ni_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);
 
 	reg = CG_R(0xffff) | CG_L(0);
-	table->initialState.levels[0].aT = cpu_to_be32(reg);
+	table->initialState.level.aT = cpu_to_be32(reg);
 
-	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
+	table->initialState.level.bSP = cpu_to_be32(pi->dsp);
 
 	if (pi->boot_in_gen2)
-		table->initialState.levels[0].gen2PCIE = 1;
+		table->initialState.level.gen2PCIE = 1;
 	else
-		table->initialState.levels[0].gen2PCIE = 0;
+		table->initialState.level.gen2PCIE = 0;
 
 	if (pi->mem_gddr5) {
-		table->initialState.levels[0].strobeMode =
+		table->initialState.level.strobeMode =
 			cypress_get_strobe_mode_settings(rdev,
 							 initial_state->performance_levels[0].mclk);
 
 		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
-			table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
+			table->initialState.level.mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
 		else
-			table->initialState.levels[0].mcFlags =  0;
+			table->initialState.level.mcFlags =  0;
 	}
 
 	table->initialState.levelCount = 1;
 
 	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
 
-	table->initialState.levels[0].dpm2.MaxPS = 0;
-	table->initialState.levels[0].dpm2.NearTDPDec = 0;
-	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
-	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
+	table->initialState.level.dpm2.MaxPS = 0;
+	table->initialState.level.dpm2.NearTDPDec = 0;
+	table->initialState.level.dpm2.AboveSafeInc = 0;
+	table->initialState.level.dpm2.BelowSafeInc = 0;
 
 	reg = MIN_POWER_MASK | MAX_POWER_MASK;
-	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
+	table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
 
 	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
-	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
+	table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
 
 	return 0;
 }
@@ -1813,43 +1813,43 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
 	if (pi->acpi_vddc) {
 		ret = ni_populate_voltage_value(rdev,
 						&eg_pi->vddc_voltage_table,
-						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
+						pi->acpi_vddc, &table->ACPIState.level.vddc);
 		if (!ret) {
 			u16 std_vddc;
 
 			ret = ni_get_std_voltage_value(rdev,
-						       &table->ACPIState.levels[0].vddc, &std_vddc);
+						       &table->ACPIState.level.vddc, &std_vddc);
 			if (!ret)
 				ni_populate_std_voltage_value(rdev, std_vddc,
-							      table->ACPIState.levels[0].vddc.index,
-							      &table->ACPIState.levels[0].std_vddc);
+							      table->ACPIState.level.vddc.index,
+							      &table->ACPIState.level.std_vddc);
 		}
 
 		if (pi->pcie_gen2) {
 			if (pi->acpi_pcie_gen2)
-				table->ACPIState.levels[0].gen2PCIE = 1;
+				table->ACPIState.level.gen2PCIE = 1;
 			else
-				table->ACPIState.levels[0].gen2PCIE = 0;
+				table->ACPIState.level.gen2PCIE = 0;
 		} else {
-			table->ACPIState.levels[0].gen2PCIE = 0;
+			table->ACPIState.level.gen2PCIE = 0;
 		}
 	} else {
 		ret = ni_populate_voltage_value(rdev,
 						&eg_pi->vddc_voltage_table,
 						pi->min_vddc_in_table,
-						&table->ACPIState.levels[0].vddc);
+						&table->ACPIState.level.vddc);
 		if (!ret) {
 			u16 std_vddc;
 
 			ret = ni_get_std_voltage_value(rdev,
-						       &table->ACPIState.levels[0].vddc,
+						       &table->ACPIState.level.vddc,
 						       &std_vddc);
 			if (!ret)
 				ni_populate_std_voltage_value(rdev, std_vddc,
-							      table->ACPIState.levels[0].vddc.index,
-							      &table->ACPIState.levels[0].std_vddc);
+							      table->ACPIState.level.vddc.index,
+							      &table->ACPIState.level.std_vddc);
 		}
-		table->ACPIState.levels[0].gen2PCIE = 0;
+		table->ACPIState.level.gen2PCIE = 0;
 	}
 
 	if (eg_pi->acpi_vddci) {
@@ -1857,7 +1857,7 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
 			ni_populate_voltage_value(rdev,
 						  &eg_pi->vddci_voltage_table,
 						  eg_pi->acpi_vddci,
-						  &table->ACPIState.levels[0].vddci);
+						  &table->ACPIState.level.vddci);
 	}
 
 
@@ -1900,37 +1900,37 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
 
-	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
-	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
-	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
-	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
-	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
-	table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
+	table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
+	table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
+	table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
+	table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
+	table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
+	table->ACPIState.level.mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
 
-	table->ACPIState.levels[0].mclk.mclk_value = 0;
+	table->ACPIState.level.mclk.mclk_value = 0;
 
-	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
-	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
-	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
-	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
+	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
+	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
+	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
+	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
 
-	table->ACPIState.levels[0].sclk.sclk_value = 0;
+	table->ACPIState.level.sclk.sclk_value = 0;
 
-	ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
+	ni_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);
 
 	if (eg_pi->dynamic_ac_timing)
-		table->ACPIState.levels[0].ACIndex = 1;
+		table->ACPIState.level.ACIndex = 1;
 
-	table->ACPIState.levels[0].dpm2.MaxPS = 0;
-	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
-	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
-	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
+	table->ACPIState.level.dpm2.MaxPS = 0;
+	table->ACPIState.level.dpm2.NearTDPDec = 0;
+	table->ACPIState.level.dpm2.AboveSafeInc = 0;
+	table->ACPIState.level.dpm2.BelowSafeInc = 0;
 
 	reg = MIN_POWER_MASK | MAX_POWER_MASK;
-	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
+	table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
 
 	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
-	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
+	table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
 
 	return 0;
 }
@@ -1980,7 +1980,9 @@ static int ni_init_smc_table(struct radeon_device *rdev)
 	if (ret)
 		return ret;
 
-	table->driverState = table->initialState;
+	table->driverState.flags = table->initialState.flags;
+	table->driverState.levelCount = table->initialState.levelCount;
+	table->driverState.levels[0] = table->initialState.level;
 
 	table->ULVState = table->initialState;
 
diff --git a/drivers/gpu/drm/radeon/nislands_smc.h b/drivers/gpu/drm/radeon/nislands_smc.h
index 7395cb6b3cac6..42f3bab0f9ee6 100644
--- a/drivers/gpu/drm/radeon/nislands_smc.h
+++ b/drivers/gpu/drm/radeon/nislands_smc.h
@@ -143,6 +143,14 @@ struct NISLANDS_SMC_SWSTATE
 
 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
 
+struct NISLANDS_SMC_SWSTATE_SINGLE {
+	uint8_t                             flags;
+	uint8_t                             levelCount;
+	uint8_t                             padding2;
+	uint8_t                             padding3;
+	NISLANDS_SMC_HW_PERFORMANCE_LEVEL   level;
+};
+
 #define NISLANDS_SMC_VOLTAGEMASK_VDDC  0
 #define NISLANDS_SMC_VOLTAGEMASK_MVDD  1
 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
@@ -160,19 +168,19 @@ typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
 
 struct NISLANDS_SMC_STATETABLE
 {
-    uint8_t                             thermalProtectType;
-    uint8_t                             systemFlags;
-    uint8_t                             maxVDDCIndexInPPTable;
-    uint8_t                             extraFlags;
-    uint8_t                             highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
-    uint32_t                            lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
-    NISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
-    PP_NIslands_DPM2Parameters          dpm2Params;
-    NISLANDS_SMC_SWSTATE                initialState;
-    NISLANDS_SMC_SWSTATE                ACPIState;
-    NISLANDS_SMC_SWSTATE                ULVState;
-    NISLANDS_SMC_SWSTATE                driverState;
-    NISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
+	uint8_t                             thermalProtectType;
+	uint8_t                             systemFlags;
+	uint8_t                             maxVDDCIndexInPPTable;
+	uint8_t                             extraFlags;
+	uint8_t                             highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
+	uint32_t                            lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
+	NISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
+	PP_NIslands_DPM2Parameters          dpm2Params;
+	struct NISLANDS_SMC_SWSTATE_SINGLE  initialState;
+	struct NISLANDS_SMC_SWSTATE_SINGLE  ACPIState;
+	struct NISLANDS_SMC_SWSTATE_SINGLE  ULVState;
+	NISLANDS_SMC_SWSTATE                driverState;
+	NISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
 };
 
 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
-- 
cgit 1.2.3-1.el7
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User avatar
Skateman
Posts: 602
Joined: Thu Aug 10, 2017 8:36 pm
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Re: Kernel 5.13

Post by Skateman »

Kernel 5.13 Alpha2 is running fine on my X5000 with R7 250 videocard.

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Big picture http://www.skateman.nl/wp-content/uploa ... 091742.png
AmigaOne X5000 -> 2GHz / 16GB RAM / Radeon R7 250 / M-Audio 5.1 -> AmigaOS 4.1 FE / Ubuntu Linux
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xeno74
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Re: Kernel 5.13

Post by xeno74 »

Skateman wrote: Fri May 07, 2021 8:19 am Kernel 5.13 Alpha2 is running fine on my X5000 with R7 250 videocard.
Thanks a lot for testing! :-)
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Skateman
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Re: Kernel 5.13

Post by Skateman »

Kernel 5.13 Alpha4 is running fine on my AmigaOne X5000

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AmigaOne X5000 -> 2GHz / 16GB RAM / Radeon R7 250 / M-Audio 5.1 -> AmigaOS 4.1 FE / Ubuntu Linux
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xeno74
Posts: 7022
Joined: Fri Mar 23, 2012 7:58 am

Re: Kernel 5.13

Post by xeno74 »

Skateman wrote: Sat May 08, 2021 7:21 pm Kernel 5.13 Alpha4 is running fine on my AmigaOne X5000
Thank you for testing the alpha4! :-)
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kilaueabart
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Re: Kernel 5.13

Post by kilaueabart »

A4 seems to work OK here,
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