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Device Tree Blobs (dtb) for the X5000
Posted: Sat Jan 20, 2018 3:25 pm
by xeno74
Hi All,
I compiled the eth dtb file with poweroff support today.
Many thanks to Sinan for the hint.
Download:
cyrus_p5020_eth_poweroff.dtb
Please test it.
Thanks,
Christian
Re: Device Tree Blobs (dtb) for the X5000
Posted: Sat Jan 20, 2018 3:32 pm
by xeno74
Source:
cyrus-pre.dtsi:
Code: Select all
/*
* P5020/P5010 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/include/ "e5500_power_isa.dtsi"
/ {
compatible = "fsl,P5020";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
pci3 = &pci3;
usb0 = &usb0;
usb1 = &usb1;
dma0 = &dma0;
dma1 = &dma1;
sdhc = &sdhc;
msi0 = &msi0;
msi1 = &msi1;
msi2 = &msi2;
crypto = &crypto;
sec_jr0 = &sec_jr0;
sec_jr1 = &sec_jr1;
sec_jr2 = &sec_jr2;
sec_jr3 = &sec_jr3;
rtic_a = &rtic_a;
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
raideng = &raideng;
raideng_jr0 = &raideng_jr0;
raideng_jr1 = &raideng_jr1;
raideng_jr2 = &raideng_jr2;
raideng_jr3 = &raideng_jr3;
fman0 = &fman0;
ethernet0 = &enet3;
ethernet1 = &enet4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
};
};
};
cyrus_p5020.dts:
Code: Select all
/*
* Cyrus 5020 Device Tree Source, based on p5020ds.dts
*
* Copyright 2015 Andy Fleming
*
* p5020ds.dts copyright:
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "cyrus-pre.dtsi"
/ {
model = "varisys,CYRUS";
compatible = "varisys,CYRUS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_3 = &phy_rgmii_3;
phy_rgmii_7 = &phy_rgmii_7;
};
memory {
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
qman_fqd: qman-fqd {
size = <0 0x400000>;
alignment = <0 0x400000>;
};
qman_pfdr: qman-pfdr {
size = <0 0x2000000>;
alignment = <0 0x2000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
qportals: qman-portals@ff4200000 {
ranges = <0x0 0xf 0xf4200000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
spi@110000 {
};
i2c@118100 {
};
i2c@119100 {
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
};
};
fman@400000 {
mdio@e1120 {
phy_rgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_rgmii_7: ethernet-phy@7 {
reg = <0x7>;
};
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_3>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_7>;
phy-connection-type = "rgmii";
};
};
};
rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>;
port1 {
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
};
port2 {
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
};
};
lbc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x1000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xffa00000 0x00040000
3 0 0xf 0xffdf0000 0x00008000>;
};
pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci2: pcie@ffe202000 {
reg = <0xf 0xfe202000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci3: pcie@ffe203000 {
reg = <0xf 0xfe203000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 3 1>;
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio0 2 1>;
};
leds {
compatible = "gpio-leds";
hdd {
label = "Disk activity";
gpios = <&gpio0 5 0>;
linux,default-trigger = "disk-activity";
};
};
};
/include/ "p5020si-post.dtsi"
Re: Device Tree Blobs (dtb) for the X5000
Posted: Sat Jan 20, 2018 3:33 pm
by xeno74
Command for building the dtb file:
Re: Device Tree Blobs (dtb) for the X5000
Posted: Sat Jan 20, 2018 4:43 pm
by Skateman
The DTB works great!!
The X5000 powers down like it should!
Thanks again!
Re: Device Tree Blobs (dtb) for the X5000
Posted: Thu Oct 17, 2019 12:06 pm
by xeno74
Hi All,
I compiled a new dtb file with poweroff support for the AmigaOne X5000/40 today.
Download:
Device_Tree_Blob_X5000_40_with_poweroff_support.tar.gz
Please test it.
Thanks,
Christian
Re: Device Tree Blobs (dtb) for the X5000
Posted: Fri Oct 18, 2019 9:50 pm
by Skateman
Tested this on my X5000 /20 just because i could
Machine did boot, DPAA Nic not probed... as expected
Re: Device Tree Blobs (dtb) for the X5000
Posted: Fri May 08, 2020 4:44 am
by xeno74
Hi All,
Darren has released new device tree blobs (dtbs) for the X5000/20 and X5000/40.
You can find them in the latest kernel package.
Download:
linux-image-5.7-rc4-X1000_X5000.tar.gz
He sent some patches to the Linux-ppc mailing today.
Link to the thread:
powerpc/mpc85xx: Define ethernet port aliases in board dts file
Many thanks to Darren!
Cheers,
Christian